1. Field of the Invention
This invention relates to the operation of a non-volatile flash memory cell and in particular, to erasing the cell by manipulating the stored charges within.
2. Description of the Related Art
U.S. Pat. No. 7,796,443 (by Danny Berco) presents that a flash Electrical Erasable Programmable Read Only Memory (EEPROM) can be erased by means of applying two time-separated voltage pulses to the semiconductor substrate and the control gate, respectively. The two-time-separated-voltage-pulse sequence in Berco has good reliability over the Negative Gate Source Erase (NGSE) sequence and faster erase speed than the conventional channel Fowler-Nordheim (F/N) tunneling. Although the conventional channel F/N tunneling method has no hot-hole injection resulting in hole-related damages in the tunneling dielectric (silicon dioxide), the tunneling process requires a long time to tunnel out the stored electrical charges (electrons or holes) from the storing material. The durations for the conventional F/N tunneling pulses are in the range of from sub-milliseconds to hundreds of milliseconds. Typically, the time required to erase a flash array to a desired threshold-voltage range using F/N tunneling can be as long as seconds depending on the applied tunneling electrical field strength (voltages across the tunneling dielectric divided by the dielectric thickness), and the properties of the storing material. The storing material can be poly-silicon; trap based dielectric film like nitride, or nano-crystals. The nitride film as charge trap material usually takes much longer time than those using poly-silicon as the storing material.
We have observed that the erase efficiency using F/N tunneling becomes very poor when the cells' threshold voltages are erased to their intrinsic threshold voltages, where the storing material stores almost zero net charges (the net charges of electrons and holes under the control gate in the channel regions). We attribute the phenomena to the interaction between the tunneling current and tunneling dielectric traps, specially the interfacial traps. In fact, the slow erase/programming behaviors of the slow-bit cells or stressed cells with higher trap density in the cell tunneling dielectric also exhibits the similar interaction. In contrast, the fast erase/programming bit cells have less trap density in the tunneling dielectric.
On the other hand, the fast erase method in Berco exhibits very large threshold voltage down-shift per erasing pulse with pulse durations of hundreds of micoseconds in contrast to the pulse durations of from several hundreds to tens of milliseconds for F/N tunneling. The pulse durations in Berco are several hundreds times shorter than those in the conventional F/N tunneling erase. Therefore, the erase speeds using the disclosed method in Berco are about two orders of magnitudes faster than the conventional F/N tunneling erase. Despite the shorter erase pulsesin Berco, we have learned that the erase method in Berco accumulates more electrons in the tunneling dielectric after numbers of program/erase cycling in comparison with conventional F/N tunneling erase. The accumulation of electrons in the tunneling dielectric reduces the erase efficiency resulting in more numbers of erase pulse shots to obtain the desired erased threshold voltages for the cycled flash cells in spite of the hundred times shorter pulse duration.
To minimize the effects of electron accumulation in the tunneling dielectric in the disclosed method of Berco and to enhance the erase efficiency for F/N tunneling near the intrinsic cell threshold voltages, we have applied a new erase sequence to incorporate both F/N tunneling pulses and the two time-separated pulses in the present invention. The new erase sequence exhibits very high erase efficiency and less electron accumulation for both fresh and program/erase cycled flash cells.